Power Consumption Benchmark
M_DCH1 EQU 10 ; DMA Active Channel 1
M_DCH2 EQU 11 ; DMA Active Channel 2
;------------------------------------------------------------------------
;
;
;
EQUATES for Phase Lock Loop (PLL)
;------------------------------------------------------------------------
Register Addresses Of PLL
M_PCTL EQU $FFFFFD; PLL Control Register
PLL Control Register
;
;
M_MF EQU $FFF
; Multiplication Factor Bits Mask (MF0-MF11)
M_DF EQU $7000 ; Division Factor Bits Mask (DF0-DF2)
M_XTLR EQU 15
M_XTLD EQU 16
M_PSTP EQU 17
M_PEN EQU 18
M_PCOD EQU 19
; XTAL Range select bit
; XTAL Disable Bit
; STOP Processing State Bit
; PLL Enable Bit
; PLL Clock Output Disable Bit
M_PD EQU $F00000; PreDivider Factor Bits Mask (PD0-PD3)
;------------------------------------------------------------------------
;
;
;
EQUATES for BIU
;------------------------------------------------------------------------
;
Register Addresses Of BIU
M_BCR EQU $FFFFFB; Bus Control Register
M_DCR EQU $FFFFFA; DRAM Control Register
M_AAR0 EQU $FFFFF9; Address Attribute Register 0
M_AAR1 EQU $FFFFF8; Address Attribute Register 1
M_AAR2 EQU $FFFFF7; Address Attribute Register 2
M_AAR3 EQU $FFFFF6; Address Attribute Register 3
M_IDR EQU $FFFFF5; ID Register
;
Bus Control Register
M_BA0W EQU $1F
M_BA1W EQU $3E0
; Area 0 Wait Control Mask (BA0W0-BA0W4)
; Area 1 Wait Control Mask (BA1W0-BA14)
M_BA2W EQU $1C00 ; Area 2 Wait Control Mask (BA2W0-BA2W2)
M_BA3W EQU $E000 ; Area 3 Wait Control Mask (BA3W0-BA3W3)
M_BDFW EQU $1F0000; Default Area Wait Control Mask (BDFW0-BDFW4)
M_BBS EQU 21
M_BLH EQU 22
M_BRH EQU 23
; Bus State
; Bus Lock Hold
; Bus Request Hold
;
DRAM Control Register
M_BCW EQU $3
M_BRW EQU $C
M_BPS EQU $300
M_BPLE EQU 11
; In Page Wait States Bits Mask (BCW0-BCW1)
; Out Of Page Wait States Bits Mask (BRW0-BRW1)
; DRAM Page Size Bits Mask (BPS0-BPS1)
; Page Logic Enable
DSP56301 Technical Data, Rev. 10
A-14
Freescale Semiconductor
FREESCALE [ Freescale ]
