86
CHAPTER 3: ELECTRICAL SPECIFICATIONS
OC-12 Timing Specifications
The OC-12 interface timing is shown in Figure 18 and described in Table 43.
Figure 18 OC-12 Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Cycle 1
CPn_1 (TCLKI)
T
c12i
T
c12d
CPn_0 (TCLK)
T
c12t
CPn+1_2-5 (Tx)
T
c12o
Cycle 1
Cycle 2
Cycle 3
CPn_1 (RCLK)
T
c12r
CPn+2_2-6 (Rx)
CPn+3_2-5 (Rx)
T
T
c12h
c12s
Table 43 OC-12 Timing Description
SYMBOL PARAMETER
MIN
TYP
MAX
60
UNIT
Tc12i
Tc12d
Tc12t
Tc12o
Tc12r
Tc12s
Tc12h
OC-12 Transmit Cycle Time*
OC-3 Clock Duty Cycle
OC-12 Transmit Cycle Time†
OC-12 Output Time‡
OC-12 Receive Cycle Time
OC-12 Setup Time
12.86
12.86
12.86
ns
%
40
ns
ns
ns
ns
ns
3.0
10.0
12.0
2.0
OC-12 Hold Time
0.0
*
Input from PHY
Output from C-3e NP
Aligned to TCLK
†
‡
C3EN
FREESCALE [ Freescale ]
