C3ENPA1-DS/D
Rev 03
Chapter 2
SIGNAL DESCRIPTIONS
Signal Summary
There are nine (9) functional groupings of signals in the C-3e Network Processor:
• Clock — 7 pins
• Channel Processors (CP0 - CP7) — 8x7 = 56 pins
• Executive Processor (XP) — 57 pins
– PCI Interface — 50 pins
– PROM Interface — 4 pins
– Serial Bus Interface — 2 pins
– General System Interface — 1 pin
• Fabric Processor (FP) — 42 pins
• Buffer Management Unit (BMU) — 160 pins
• Table Lookup Unit (TLU) — 99 pins
• Queue Management Unit (QMU) — 59 pins
• Power — 234 pins
• Test — 14 pins
Two (2) of the sections (CPs and FP) are configurable, depending on the type of device
being implemented.
03
FREESCALE [ Freescale ]
