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C5EC3EARCH-RM/D 参数 Datasheet PDF下载

C5EC3EARCH-RM/D图片预览
型号: C5EC3EARCH-RM/D
PDF下载: 下载PDF文件 查看货源
内容描述: C- 3E网络处理器芯片版本A1 [C-3e NETWORK PROCESSOR SILICON REVISION A1]
分类和应用:
文件页数/大小: 114 页 / 2056 K
品牌: FREESCALE [ Freescale ]
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CHAPTER 1: FUNCTIONAL DESCRIPTION  
PROM Interface Allows the XP to boot from nonvolatile, flash memory. The PROM  
interface is a low-speed, serial I/O port that runs at 1/2 to 1/16 the core clock rate. The  
maximum PROM size addressable is 4MBytes, and must use a by 16part. External  
board logic is required to perform serial-to-parallel conversion for PROM address  
outputs and parallel-to-serial conversion for PROM data inputs.  
Fabric Processor  
The Fabric Processor (FP) acts as a high-speed network interface port with advanced  
functionality. It allows the C-3e NP to interface to an application-specific switching  
solution internal to your design. The FP port supports the bidirectional transfer of  
segments from the C-3e NP to a hardware interface that provides connectivity to other  
network processors or other similar line processing hardware. There are numerous  
parameters that can be configured within the FP to allow the interface to be adapted to  
different fabric protocols. The FP can be configured to conform to three (3) different fabric  
interfaces that include: UTOPIA-1, -2, -3.  
The FP can be configured to run at any frequency up to 125MHz, with the receive and  
transmit data buses up to 16 bits wide. This allows a wide range of supported bandwidths  
to and from the switching fabric, all the way up to 2000 Mbps full duplex bandwidth.  
Buffer Management Unit  
The Buffer Management Unit (BMU) interfaces the C-3e NP to external pipeline  
architecture, Single Data Rate Synchronous DRAM. The external memory is partitioned  
and used as buffers for receiving and transmitting data between CPs, the FP, and the XP. It  
is also used as second level storage in the XP memory hierarchy.  
The interface to an array of SDRAM chips is 139bits wide, composed of 128 data bits, two  
internal control bits, and nine SECDED (single error correction-double error detection) ECC  
(error correction code) bits. The interface is compliant with the PC100 standard and  
operates at up to 125MHz with 3.3V LVTTL-compatible inputs and outputs. The refresh  
period, Trcd, Tcas, Trp, Tmrd, and Trc are configurable via boot time configuration (see the  
C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM/D) for more  
details).  
The C-3e NP non-configurable interface transfers four beats of data for each read and  
write using a sequential burst type. In addition, the C-3e NP uses an auto-refresh mode for  
the RAMs.  
C3EN