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C5EC3EARCH-RM/D 参数 Datasheet PDF下载

C5EC3EARCH-RM/D图片预览
型号: C5EC3EARCH-RM/D
PDF下载: 下载PDF文件 查看货源
内容描述: C- 3E网络处理器芯片版本A1 [C-3e NETWORK PROCESSOR SILICON REVISION A1]
分类和应用:
文件页数/大小: 114 页 / 2056 K
品牌: FREESCALE [ Freescale ]
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CHAPTER 1: FUNCTIONAL DESCRIPTION  
Channel Processors  
The C-3e NP contains eight programmable external Channel Processors (CPs) that receive,  
process, and transmit network data, plus an additional eight internal CPs that process  
data. Typically one CP is assigned to each port for medium bandwidth applications (Fast  
Ethernet to OC-3). Multiple CPs can be assigned to a port in a configuration called channel  
aggregation in high bandwidth applications (greater than OC-3). Multiple logical ports  
can be assigned to a single CP, with the addition of an external multiplexor, for low  
bandwidth applications, such as DS1 to DS3.  
The C-3e NPs architecture supports a variety of industry-standard serial and parallel  
protocols and individual port data rates including:  
10/100Mb Ethernet (RMII)  
1Gb Ethernet (GMII and TBI)  
OC-3c  
OC-12  
100Mbit FibreChannel  
DS1/DS3, supported through the use of external framers/multiplexors  
The C-3e NP’s programmability can also support a variety of special interfaces, such as  
various xDSL encapsulations and proprietary protocols.  
Key components of each CP are a RISC Core (CPRC) that orchestrates cell/packet  
processing and a set of microprogrammable, special-purpose processors, called Serial  
Data Processors (SDPs), that provide features such as Ethernet MAC and SONET/SDH  
framing, multichannel HDLC, and ATM cell delineation. This means you usually only need  
to include PHYs to complete the system.  
C3EN