Freescale Semiconductor, Inc.
AN2528/D
Detailed Function Description
Table 10. svmStd_bottom State Statistics
State
C1
C2
C3
C4
Max IMB Clock Cycles
RAM Accesses by TPU
48
48
50
48
3
4
3
8
NOTE:
Execution times do not include the time slot transition time (TST = 10 or 14 IMB
clocks)
HL
LH_C5
HL
HL
LH_C5
- top
Phase A
LH
L
L
H
H
HL
HL
- bottom
HL
LH_C5
H
H
L
L
LH_C5
LH_C5
- top
Phase B
- bottom
H
H
L
L
HL
HL
LH
H
LH
LH
HL
LH_C5
H
H
L
L
LH_C5
- top
Phase C
- bottom
LH_RLD
H
H
L
L
LH_RLD
C1
C2
C3
C4
HL
HL
flag0 = 1
center_time
T
center_time
center_time
T
T
n
n
o
o
t
t
a
a
r
r
e
e
l
l
o
o
a
a
d
d
p
p
e
e
r
r
i
i
o
o
d
d
reload period
reload period
Figure 3. svmStd_top and svmStd_bottom timing
NOTE:
The bottom channel with longest momentary low-time is marked by a flag0 and
runs the LH_RLD and C1, C2, C3, C4 states.
Standard Space Vector Modulation TPU Function Set (svmStd)
11
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