Freescale Semiconductor, Inc.
Figure 3-22 is a flowchart showing bus arbitration for a single device. This technique
allows processing of bus requests during data transfer cycles. Refer to Figures 3-23 and
3-24 for bus arbitration timing diagrams.
BR is negated at the time that BGACK is asserted. This type of operation applies to a
system consisting of the MC68340 and one device capable of bus mastership. In a system
having a number of devices capable of bus mastership, BR from each device can be wire-
ORed to the MC68340. In such a system, more than one bus request could be asserted
simultaneously. BG is negated a few clock cycles after the transition of BGACK. However,
if bus requests are still pending after the negation of BG, the MC68340 asserts another BG
within a few clock cycles after it was negated. This additional assertion of BG allows
external arbitration circuitry to select the next bus master before the current bus master
has finished using the bus. The following paragraphs provide additional information about
the three steps in the arbitration process. Bus arbitration requests are recognized during
normal processing, HALT assertion, and a CPU32 halt caused by a double bus fault.
PROCESSOR
REQUESTING DEVICE
REQUEST THE BUS
1. ASSERT BR
GRANT BUS ARBITRATION
1. ASSERT BG
ACKNOWLEDGE BUS MASTERSHIP
1. EXTERNAL ARBITRATION DETERMINES
NEXT BUS MASTER
2. NEXT BUS MASTER WAITS FOR BGACK
TO BE NEGATED
3. NEXT BUS MASTER ASSERTS BGACK
TO BECOME NEW MASTER
TERMINATE ARBITRATION
4. BUS MASTER NEGATES BR
1. NEGATE BG (AND WAIT FOR
BGACK TO BE NEGATED)
OPERATE AS BUS MASTER
1. PERFORM DATA TRANSFERS (READ AND
WRITE CYCLES) ACCORDING TO THE
SAME RULES THE PROCESSOR USES
RELEASE BUS MASTERSHIP
1. NEGATE BGACK
RE-ARBITRATE OR RESUME
PROCESSOR OPERATION
Figure 3-22. Bus Arbitration Flowchart for Single Request
MOTOROLA
MC68340 USER’S MANUAL
3- 41
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