Freescale Semiconductor, Inc.
S0
S2
SW
SW
S4
S0
S2
S4
CLKOUT
A31–A0
FC3–FC0
R/W
AS
DS
DSACKx
DATA
IGNORED
D15–D0
BERR
HALT
READ CYCLE WITH
RETRY
HALT
READ RERUN
Figure 3-19. Retry Sequence
The MC68340 retries any read or write cycle of a read-modify-write operation separately;
RMC remains asserted during the entire retry sequence. Asserting BR along with BERR
and HALT provides a relinquish and retry operation. The MC68340 does not relinquish the
bus during a read-modify-write operation. Any device that requires the MC68340 to give
up the bus and retry a bus cycle during a read-modify-write cycle must assert only BERR
and BR (HALT must not be included). The bus error handler software should examine the
read-modify-write bit in the special status word (see Section 5 CPU32) and take the
appropriate action to resolve this type of fault when it occurs.
MOTOROLA
MC68340 USER’S MANUAL
3- 37
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
