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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
If a system asserts DSACKfor the required window around the falling edge of S2 and  
obeys the proper bus protocol by maintaining DSACK(and/or BERR/HALT) until and  
throughout the clock edge that negates AS (with the appropriate asynchronous input hold  
time), no wait states are inserted. The bus cycle runs at its maximum speed for bus cycles  
terminated with DSACK(three clocks per cycle). When BERR (or BERR and HALT) is  
asserted after DSACK, BERR (and HALT) must meet the appropriate setup time prior to  
the falling clock edge one clock cycle after DSACKis recognized. This setup time is  
critical, and the MC68340 may exhibit erratic behavior if it is violated. When operating  
synchronously, the data-in setup and hold times for synchronous cycles may be used  
instead of the timing requirements for data relative to DS.  
3.2.6 Fast Termination Cycles  
With an external device that has a fast access time, the chip select circuit fast termination  
enable (FTE) can provide a two-clock external bus transfer. Since the chip select circuits  
are driven from the system clock, the bus cycle termination is inherently synchronized with  
the system clock. Refer to Section 4 System Integration Module for more information on  
chip selects.When fast termination is selected, the DD bits of the corresponding address  
mask register are overridden. Fast termination can only be used with zero wait states. To  
use the fast termination option, an external device should be fast enough to have data  
ready, within the specified setup time, by the falling edge of S4. Figure 3-6 shows the  
DSACKtiming for a read with two wait states, followed by a fast termination read and  
write. When using the fast termination option, DS is asserted only in a read cycle, not in a  
write cycle.  
S0 S1 S2 S3 SW SW SW SW S4 S5 S0 S1 S4 S5 S0 S1 S4 S5 S0  
*
*
CLKOUT  
AS  
DS  
R/W  
DSACKx  
D15–D0  
FAST  
TERMINATION  
READ  
TWO WAIT STATES IN READ  
FAST  
TERMINATION  
WRITE  
* DSACKx only internally asserted for fast termination cycles.  
Figure 3-6. Fast Termination Timing  
MOTOROLA  
MC68340 USER’S MANUAL  
3- 15  
For More Information On This Product,  
Go to: www.freescale.com  
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