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AN1063D 参数 Datasheet PDF下载

AN1063D图片预览
型号: AN1063D
PDF下载: 下载PDF文件 查看货源
内容描述: 集成的处理器与DMA USERA ????手册 [Integrated Processor with DMA User’s Manual]
分类和应用:
文件页数/大小: 441 页 / 2488 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
3.3.2 Write Cycle  
During a write cycle, the MC68340 transfers data to memory or a peripheral device. Figure  
3-8 is a flowchart of a word write cycle.  
BUS MASTER  
SLAVE  
ADDRESS DEVICE  
1. SET R/W TO WRITE  
2. DRIVE ADDRESS ON A31–A0  
3. DRIVE FUNCTION CODE ON FC3–FC0  
4. DRIVE SIZE PINS FOR OPERAND SIZE  
5. ASSERT AS  
6. PLACE DATA ON D15–D0  
7. ASSERT DS  
ACCEPT DATA  
1. DECODE ADDRESS  
2. LATCH DATA FROM D15–D0  
3. ASSERT DSACKx SIGNALS  
TERMINATE OUTPUT TRANSFER  
1. NEGATE DS AND AS  
2. REMOVE DATA FROM D15–D0  
TERMINATE CYCLE  
1. NEGATE DSACKx  
START NEXT CYCLE  
Figure 3-8. Word Write Cycle Flowchart  
State 0—The write cycle starts in S0. During S0, the MC68340 places a valid address on  
A31–A0 and valid function codes on FC3–FC0. The function codes select the address  
space for the cycle. The MC68340 drives R/W low for a write cycle. SIZ1/SIZ0 become  
valid, indicating the number of bytes to be transferred.  
State 1—One-half clock later during S1, the MC68340 asserts AS, indicating a valid  
address on the address bus.  
State 2—During S2, the MC68340 places the data to be written onto D15–D0, and  
samples DSACKat the end of S2.  
State 3—The MC68340 asserts DS during S3, indicating that data is stable on the data  
bus. As long as at least one of the DSACKsignals is recognized by the end of S2  
(meeting the asynchronous input setup time requirement), the cycle terminates one clock  
later. If DSACKis not recognized by the start of S3, the MC68340 inserts wait states  
instead of proceeding to S4 and S5. To ensure that wait states are inserted, both  
DSACK1 and DSACK0 must remain negated throughout the asynchronous input setup  
and hold times around the end of S2. If wait states are added, the MC68340 continues to  
sample DSACKon the falling edges of the clock until one is recognized. The selected  
device uses R/W, SIZ1/SIZ0, and A0 to latch data from the appropriate byte(s) of D15–D8  
and D7–D0. SIZ1/SIZ0 and A0 select the bytes of the data bus. If it has not already done  
so, the device asserts DSACKto signal that it has successfully stored the data.  
3- 18  
MC68340 USER’S MANUAL  
MOTOROLA  
For More Information On This Product,  
Go to: www.freescale.com  
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