Freescale Semiconductor, Inc.
Table 9-2. Boundary Scan Bit Definitions
Bit
Pin/Cell
Name
Pin
Type
Output
CTL Cell
Bit
Pin/Cell
Name
Pin
Type
Output
CTL Cell
Num Cell Type
Num Cell Type
0
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
IO.Cell
I.Pin
FC3
FC2
FC1
FC0
A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
I/O*
I/O*
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
ab.ctl
—
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
O.Latch
O.Latch
I.Pin
R≈RDYA
T≈RDYA
RxDB
TxDB
RTSB
CTSB
SCLK
X1
Output
Output
Input
Output
Output
Input
Input
Input
Input
Output
OD-I/O
OD-I/O
Input
Output
OD-I/O
OD-I/O
I/O
—
—
1
2
I/O*
—
3
I/O*
O.Latch
O.Latch
I.Pin
—
4
I/O*
—
5
I/O*
—
6
I/O*
I.Pin
—
7
I/O*
I.Pin
—
8
I/O*
I.Pin
DREQ1
DACK1
DONE1
DONE1
DREQ2
DACK2
DONE2
DONE2
IRQ7
—
9
I/O*
O.Latch
O.Latch
I.Pin
—
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
I/O*
—
I/O*
—
I/O*
I.Pin
—
I/O*
O.Latch
O.Latch
I.Pin
—
I/O*
—
I/O*
—
I/O*
IO.Cell
IO.Ctl0
IO.Cell
IO.Ctl0
IO.Cell
IO.Ctl0
IO.Cell
IO.Ctl0
IO.Cell
IO.Ctl0
IO.Cell
IO.Ctl0
IO.Cell
IO.Ctl0
IO.Cell
IO.Ctl0
IO.Cell
IO.Cell
IO.Cell
irq7.ctl
—
I/O*
irq7.ctl
IRQ6
—
I/O*
I/O
irq6.ctl
—
A8
I/O*
irq6.ctl
IRQ5
—
A7
I/O*
I/O
irq5.ctl
—
A6
I/O*
irq5.ctl
CS3
—
A5
I/O*
I/O
cs3.ctl
—
A4
I/O*
cs3.ctl
IRQ3
—
A3
I/O*
I/O
irq3.ctl
—
A2
I/O*
irq3.ctl
CS2
—
A1
I/O*
I/O
cs2.ctl
—
TGATE2
TOUT2
tout2.ctl
TIN2
RxDA
TxDA
RTSA
CTSA
Input
TS-Output
—
cs2.ctl
CS1
—
O.Latch
IO.Ctl0
I.Pin
tout2.ctl
—
I/O
cs1.ctl
—
cs1.ctl
CS0
—
Input
Input
Output
Output
Input
—
I/O
cs0.ctl
—
I.Pin
—
cs0.ctl
D0
—
O.Latch
O.Latch
I.Pin
—
I/O
db.ctl
db.ctl
db.ctl
—
D1
I/O
—
D2
I/O
MOTOROLA
MC68340 USER’S MANUAL
9- 5
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