Freescale Semiconductor, Inc.
SECTION 9
IEEE 1149.1 TEST ACCESS PORT
The MC68340 includes dedicated user-accessible test logic that is fully compatible with
the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems
associated with testing high-density circuit boards have led to development of this
proposed standard under the sponsorship of the Test Technology Committee of IEEE and
the Joint Test Action Group (JTAG). The MC68340 implementation supports circuit-board
test strategies based on this standard.
The test logic includes a test access port (TAP) consisting of four dedicated signal pins, a
16-state controller, an instruction register, and two test data registers. A boundary scan
register links all device signal pins into a single shift register. The test logic, implemented
using static logic design, is independent of the device system logic. The MC68340
implementation provides the following capabilities:
a. Perform boundary scan operations to test circuit-board electrical continuity
b. Sample the MC68340 system pins during operation and transparently shift
out the result in the boundary scan register
c. Bypass the MC68340 for a given circuit-board test by effectively reducing the
boundary scan register to a single bit
d. Disable the output drive to pins during circuit-board testing
NOTE
Certain precautions must be observed to ensure that the IEEE
1149.1 test logic does not interfere with nontest operation. See
9.6 Non-IEEE 1149.1 Operation for details.
9.1 OVERVIEW
NOTE
This description is not intended to be used without the
supporting IEEE 1149.1 document.
The discussion includes those items required by the standard and provides additional
information specific to the MC68340 implementation. For internal details and applications
of the standard, refer to the IEEE 1149.1 document.
MOTOROLA
MC68340 USER’S MANUAL
9- 1
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