Freescale Semiconductor, Inc.
* Timer1 register offsets from timer1 base address
IR1
CR1
SR1
CNTR1
COM1
EQU $604
EQU $606
EQU $608
EQU $60A
EQU $610
interrupt register timer1
control register timer1
status register timer1
counter register timer1
compare register timer1
***************************************************************************
***************************************************************************
* Initialize Timer1
***************************************************************************
LEA MODBASE+TIMER1,A0 Pointer to timer1 module
* Disable timer1
CLR.W
CR1(A0)
* Allow TGATE to negate and assert so that an accurate count will result.
* If SR1 TGL bit=1, continue looping. TGATE is negated.
LOOP1
BNE.B
BTST.B
LOOP1
#$3,SR1(A0)
* If TGL bit=0, continue looping. TGATE is asserted.
LOOP2
BEQ.B
BTST.B
LOOP2
#$3,SR1(A0)
* Ready to initialize timer1, TGATE is negated.
* Module configuration register:
* Timer1 module is set for normal operation, ignore FREEZE.
* Supervisor/user timer1 registers unrestricted.
* Interrupt arbitration at priority $03.
MOVE.W
#$0003,MCR1(A0)
* Initialize timer1 interrupt level to 2 and vector to $0F
MOVE.W #$020F,IR1(A0)
* Initialize the compare register to 0
CLR.W COM1(A0)
* Clear the SR1 TG bit (by writing a 1) to use as a flag
MOVE.B
#$20,SR1(A0)
* Control register 1:
* Enable timer1, no interrupts are enabled, TGATE signal used to control
* the counter. Use the selected clock for the counter clock, and enable it.
* Selected clock is 1/2 system's freq. Pulse-width measurement,
* disable TOUT.
8- 30
MC68340 USER’S MANUAL
MOTOROLA
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
