Freescale Semiconductor, Inc.
NOTE
All serial module registers are only accessible as bytes. The
contents of the mode registers (MR1 and MR2), clock-select
register (CSR), and the auxiliary control register (ACR) bit 7
should only be changed after the receiver/transmitter is issued
a software RESET command—i.e., channel operation must be
disabled. Care should also be taken if the register contents are
changed during receiver/transmitter operations, as undesirable
results may be produced.
In the registers discussed in the following pages, the numbers in the upper right-hand
corner indicate the offset of the register from the base address specified in the module
base address register (MBAR) in the SIM40. The numbers above the register description
represent the bit position in the register. The register description contains the mnemonic
for the bit. The values shown below the register description are the values of those
register bits after a hardware reset. A value of U indicates that the bit value is unaffected
by reset. The read/write status and the access privilege are shown in the last line.
NOTE
A CPU32 RESET instruction will not affect the MCR, but will
reset all the other serial module registers as though a
hardware reset had occurred. The module is enabled when the
STP bit in the MCR is cleared. The module is disabled when
the STP bit in the MCR is set.
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MC68340 USER’S MANUAL
MOTOROLA
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