Freescale Semiconductor, Inc.
Table 4-8. BMTx Encoding
BMT1
BMT0
Bus Monitor Timeout Period
64 system clocks (CLKOUT)
32 system clocks
0
0
1
1
0
1
0
1
16 system clocks
8 system clocks
4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the
interrupt level and the vector number for the periodic interrupt request. This register can
be read or written at any time. Bits 15–11 are unimplemented and always return zero; a
write to these bits has no effect.
PICR
$022
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
PIRQL2 PIRQL1 PIRQL0
PIV7
PIV6
PIV5
PIV4
PIV3
PIV2
PIV1
PIV0
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
Supervisor Only
Bits 15–11—Reserved
PIRQL2–PIRQL0—Periodic Interrupt Request Level
These bits contain the periodic interrupt request level. Table 4-9 lists which interrupt
request level is asserted during an IACK cycle when a periodic interrupt is generated.
The periodic timer continues to run when the interrupt is disabled.
Table 4-9. PIRQL Encoding
PIRQL2
PIRQL1
PIRQL0
Interrupt Request Level
Periodic Interrupt Disabled
Interrupt Request Level 1
Interrupt Request Level 2
Interrupt Request Level 3
Interrupt Request Level 4
Interrupt Request Level 5
Interrupt Request Level 6
Interrupt Request Level 7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NOTE:
Use caution with a level 7 interrupt encoding due to the
SIM40's interrupt servicing order. See 4.2.2.7 Simultaneous
Interrupts by Sources in the SIM40 for the servicing order.
4- 26
MC68340 USER’S MANUAL
MOTOROLA
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