Freescale Semiconductor, Inc.
LOC—Loss of Clock Reset
1 = The last reset was caused by a loss of frequency reference to the clock
synthesizer. This reset can only occur if the RSTEN bit in the SYNCR is set and
the VCO is enabled.
SYS—System Reset
1 = The last reset was caused by the CPU32 executing a RESET instruction. The
system reset does not load a reset vector or affect any internal CPU32 registers,
SIM40 configuration registers, or the MCR in each internal peripheral module
(DMA, timers, and serial modules). It will, however, reset external devices and all
other registers in the peripheral modules.
4.3.2.4 SOFTWARE INTERRUPT VECTOR REGISTER (SWIV). The SWIV contains the
8-bit vector that is returned by the SIM40 during an IACK cycle in response to an interrupt
generated by the software watchdog. This register can be read or written at any time. This
register is set to the uninitialized vector, $0F, at reset.
SWIV
$020
7
6
5
4
3
2
1
0
SWIV7 SWIV6 SWIV5 SWIV4 SWIV3 SWIV2 SWIV1 SWIV0
RESET:
0
0
0
0
1
1
1
1
Supervisor Only
4.3.2.5 SYSTEM PROTECTION CONTROL REGISTER (SYPCR). The SYPCR controls
the system monitors, the prescaler for the software watchdog, and the bus monitor timing.
This register can be read at any time, but can be written only once after reset.
SYPCR
$021
0
7
6
5
4
3
2
1
SWE
SWRI
SWT1
SWT0
DBFE
BME
BMT1
BMT0
RESET:
0
0
0
0
0
0
0
0
Supervisor Only
SWE—Software Watchdog Enable
1 = Software watchdog is enabled.
0 = Software watchdog is disabled.
See 4.2.2.5 Software Watchdog for more information.
SWRI—Software Watchdog Reset/Interrupt Select
1 = Software watchdog causes a system reset.
0 = Software watchdog causes a level 7 interrupt to the CPU32.
4- 24
MC68340 USER’S MANUAL
MOTOROLA
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