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SWT1, SWT0—Software Watchdog Timing
These bits, along with the SWP bit in the PITR, control the divide ratio used to establish
the timeout period for the software watchdog. The software watchdog timeout period is
given by the following formula:
divide count
EXTAL frequency
The software watchdog timeout period, listed in Table 4-7, gives the formula to derive the
software watchdog timeout for any clock frequency. The timeout periods are listed for a
32.768-kHz crystal used with the VCO and for a 16.777-MHz external oscillator.
Table 4-7. Deriving Software Watchdog Timeout
32.768-kHz
Crystal Period
16.777-MHz External
Clock Period
SWP
SWT1 SWT0
Software Timeout Period
9
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
2 /EXTAL Input Frequency
15.6 ms
62.5 ms
250 ms
1 s
30 µs
122 µs
488 µs
1.95 ms
15.6 ms
62.5 ms
250 ms
1 s
11
2
/EXTAL Input Frequency
/EXTAL Input Frequency
/EXTAL Input Frequency
/EXTAL Input Frequency
/EXTAL Input Frequency
/EXTAL Input Frequency
/EXTAL Input Frequency
13
2
15
2
18
2
8 s
20
2
32 s
22
2
128 s
512 s
24
2
NOTE: When the SWP and SWT bits are modified to select a software timeout other than the default, the
software service sequence ($55 followed by $AA written to the software service register) must be
performed before the new timeout period takes effect. Refer to 4.2.2.5 Software Watchdog for
more information.
DBFE—Double Bus Fault Monitor Enable
1 = Enable double bus fault monitor function.
0 = Disable double bus fault monitor function.
For more information, see 4.2.2.3 Double Bus Fault Monitor and Section 5 CPU32.
BME—Bus Monitor External Enable
1 = Enable bus monitor function for an internal-to-external bus cycle.
0 = Disable bus monitor function for an internal-to-external bus cycle.
For more information see 4.2.2.2 Internal Bus Monitor.
BMT1, BMT0—Bus Monitor Timing
These bits select the timeout period for the bus monitor (see Table 4-8). Upon reset, the
bus monitor is set to 64 system clocks.
MOTOROLA
MC68340 USER’S MANUAL
4- 25
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