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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Pinout and Signal Descriptions  
Port Signals  
3.5.12 Port P  
The four pulse-width modulation channel outputs share general-purpose  
port P pins. The PWM function is enabled with the PWEN register.  
Enabling PWM pins takes precedence over the general-purpose port.  
When pulse-width modulation is not in use, the port pins may be used for  
general-purpose I/O.  
Register DDRP determines pin direction of port P when used for  
general-purpose I/O. When DDRP bits are set, the corresponding pin is  
configured for output. On reset the DDRP bits are cleared and the  
corresponding pin is configured for input.  
When the PUPP bit in the PWCTL register is set, all input pins are pulled  
up internally by an active pull-up device. Pull-ups are disabled after reset.  
Setting the RDPP bit in the PWCTL register configures all port P outputs  
to have reduced drive levels. Levels are at normal drive capability after  
reset. The PWCTL register can be read or written anytime after reset.  
Refer to Pulse Width Modulator.  
3.5.13 Port S  
Port S is the 8-bit interface to the standard serial interface consisting of  
the two serial communications interfaces (SCI1 and SCI0) and the serial  
peripheral interface (SPI) subsystems. Port S pins are available for  
general-purpose I/O when standard serial functions are not enabled.  
Port S pins serve several functions depending on the various internal  
control registers. If WOMS bit in the SC0CR1register is set, the P-  
channel drivers of the output buffers are disabled (wire-or mode) for pins  
0 through 3. If SWOM bit in the SP0CR1 register is set, the P-channel  
drivers of the output buffers are disabled (wire-or mode) for pins 4  
through 7. The open drain control affects both the serial and the general-  
purpose outputs. If the RDPS bit in the SP0CR2 register is set, Port S  
pin drive capabilities are reduced. If PUPS bit in the SP0CR2 register is  
set, a pull-up device is activated for each port S pin programmed as a  
general purpose input. If the pin is programmed as a general-purpose  
output, the pull-up is disconnected from the pin regardless of the state of  
PUPS bit. See Multiple Serial Interface.  
MC68HC912DG128 — Rev 3.0  
Technical Data  
Pinout and Signal Descriptions  
For More Information On This Product,  
Go to: www.freescale.com  
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