Freescale Semiconductor, Inc.
Enhanced Capture Timer
Introduction
÷ 1, 2, ..., 128
16-bit Free-running
16-bit load register
Prescaler
M clock
16 BIT MAIN TIMER
main timer
÷ 1, 4, 8, 16
16-bit modulus
down counter
Prescaler
M clock
RESET
0
Comparator
w
PT0
Pin logic
Pin logic
Pin logic
Pin logic
Pin logic
o
TC0 capture/compare register
Delay counter
PAC0
EDG0
EDG1
EDG2
EDG3
n
U
TC0H hold register
PA0H hold register
RESET
0
Comparator
PT1
PT2
PT3
TC1 capture/compare register
PAC1
Delay counter
Delay counter
Delay counter
TC1H hold register
PA1H hold register
RESET
0
Comparator
TC2 capture/compare register
PAC2
TC2H hold register
PA2H hold register
RESET
0
Comparator
TC3 capture/compare register
PAC3
TC3H hold register
PA3H hold register
Comparator
PT4
PT5
EDG4
EDG0
TC4 capture/compare register
MUX
MUX
ICLAT, LATQ, BUFEN
(force latch)
Comparator
Pin logic
Pin logic
Pin logic
EDG5
EDG1
TC5 capture/compare register
Write $0000
to modulus counter
LATQ
(MDC latch enable)
Comparator
PT6
PT7
EDG6
EDG2
TC6 capture/compare register
MUX
MUX
Comparator
EDG7
EDG3
TC7 capture/compare register
Figure 13-1. Timer Block Diagram in Latch Mode
MC68HC912DG128 — Rev 3.0
Technical Data
Enhanced Capture Timer
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