Freescale Semiconductor, Inc.
Enhanced Capture Timer
Introduction
Load holding register and reset pulse accumulator
0
EDG0
8-bit PAC0 (PACN0)
PT0
PT1
PT2
PT3
Edge detector
Edge detector
Edge detector
Edge detector
Delay counter
Delay counter
Delay counter
Delay counter
PA0H holding register
Interrupt
0
0
0
EDG1
8-bit PAC1 (PACN1)
PA1H holding register
8-bit PAC2 (PACN2)
EDG2
PA2H holding register
8-bit PAC3 (PACN3)
Interrupt
EDG3
PA3H holding register
Figure 13-3. 8-Bit Pulse Accumulators Block Diagram
MC68HC912DG128 — Rev 3.0
Technical Data
Enhanced Capture Timer
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