Freescale Semiconductor, Inc.
Clock Functions
FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset
Writes are not allowed in normal modes, anytime in special modes.
Read anytime.
If DISR is set, this bit has no effect.
0 = Normal operation.
1 = A clock monitor failure reset or a COP failure reset is forced
depending on the state of CME and if COP is enabled.
CME
COP enabled
Forced reset
none
0
0
1
1
0
1
0
1
COP failure
Clock monitor failure
Both(1)
1. Highest priority interrupt vector is serviced.
WCOP — Window COP mode
Write once in normal modes, anytime in special modes. Read
anytime.
0 = Normal COP operation
1 = Window COP operation
When set, a write to the COPRST register must occur in the last 25%
of the selected period. A premature write will also reset the part. As
long as all writes occur during this window, $55 can be written as often
as desired. Once $AA is written the time-out logic restarts and the
user must wait until the next window before writing to COPRST.
Please note, there is a fixed time uncertainty about the exact COP
counter state when reset, as the initial prescale clock divider in the
RTI section is not cleared when the COP counter is cleared. This
means the effective window is reduced by this uncertainty. Table 11-
5 below shows the exact duration of this window for the seven
available COP rates.
Technical Data
MC68HC912DG128 — Rev 3.0
Clock Functions
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