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68HC912DG128PV8 参数 Datasheet PDF下载

68HC912DG128PV8图片预览
型号: 68HC912DG128PV8
PDF下载: 下载PDF文件 查看货源
内容描述: M68HC12微控制器 [M68HC12 Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 452 页 / 3509 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Clock Functions  
Limp-Home and Fast STOP Recovery modes  
improper EXTALi clock cycles can occur on SYSCLK. This may lead to  
a code runaway.  
11.6.7 STOP exit in Limp Home mode without Delay (Fast Stop Recovery)  
(NOLHM=0, CME=X, DLY=0)  
Fast STOP recovery refers to any exit from STOP using DLY=0.  
If the NOLHM bit is cleared, then the CME (or FCME) bit is masked when  
a STOP instruction is executed to prevent a clock monitor failure. When  
coming out of STOP mode, the MCU goes into limp-home mode where  
CME and FCME signals are asserted.  
When using a crystal oscillator, it is possible to exit STOP with the DLY  
bit cleared. In this case, STOP is de-asserted without delay and the MCU  
will execute software in limp-home mode, giving the crystal oscillator  
time to stablise.  
CAUTION: This mode is not recommended since the risk of the clock monitor  
detecting incorrect clocks is high.  
Each time the 13-stage counter reaches a count of 4096 XCLK cycles  
(every 8192 cycles), a check of the clock monitor status is performed. If  
the clock monitor indicates the presence of an external clock limp-home  
mode is de-asserted, the LHOME flag is cleared and the limp-home  
interrupt flag is set. Upon leaving limp-home mode, BCSP and MCS are  
restored to their values before the loss of clock, and all clocks return to  
their previous frequencies. If AUTO and BCSP were set before the clock  
loss, the SYSCLK ramps-up and the PLL locks at the previously selected  
frequency.  
To prevent PLL operation when the external clock frequency comes  
back, the software should clear the BCSP bit while running in limp-home  
mode.  
When using an external clock, i.e. a square wave source, it is possible  
to exit STOP with the DLY bit cleared. In this case the LHOME flag is  
never set and STOP is de-asserted without delay.  
MC68HC912DG128 — Rev 3.0  
Technical Data  
Clock Functions  
For More Information On This Product,  
Go to: www.freescale.com  
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