Freescale Semiconductor, Inc.
I/O Ports with Key Wake-up
KWIFJ — Key Wake-up Port J Flag Register
$002E
Bit 7
KWIFJ7
0
6
KWIFJ6
0
5
KWIFJ5
0
4
KWIFJ4
0
3
KWIFJ3
0
2
KWIFJ2
0
1
KWIFJ1
0
Bit 0
KWIFJ0
0
RESET:
Read and write anytime.
Each flag is set by an active edge on its associated input pin. This could
be a rising or falling edge based on the state of the KWPJ register. To
clear the flag, write one to the corresponding bit in KWIFJ.
Initialize this register after initializing KWPJ so that illegal flags can be
cleared.
KWIFJ[7:0] — Key Wake-up Port J Flags
0 = Active edge on the associated bit has not occurred
1 = Active edge on the associated bit has occurred (an interrupt will
occur if the associated enable bit is set).
Bit 7
KWIFH7
0
6
KWIFH6
0
5
KWIFH5
0
4
KWIFH4
0
3
KWIFH3
0
2
KWIFH2
0
1
KWIFH1
0
Bit 0
KWIFH0
0
RESET:
KWIFH — Key Wake-up Port H Flag Register
$002F
Read and write anytime.
Each flag is set by an active edge on its associated input pin. This could
be a rising or falling edge based on the state of the KWPH register. To
clear the flag, write one to the corresponding bit in KWIFH.
Initialize this register after initializing KWPH so that illegal flags can be
cleared.
KWIFH[7:0] — Key Wake-up Port H Flags
0 = Active edge on the associated bit has not occurred
1 = Active edge on the associated bit has occurred (an interrupt will
occur if the associated enable bit is set)
Technical Data
MC68HC912DG128 — Rev 3.0
I/O Ports with Key Wake-up
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
