Freescale Semiconductor, Inc.
EEPROM Memory
8.5 EEPROM Control Registers
EEMCR — EEPROM Module Configuration
$00F0
Bit 7
6
5
1(1)
4
1(1)
3
1
1
2
1
Bit 0
EERC
0
NOBDML
NOSHB
EESWAI PROTLCK
(2)
(2)
(2)
(2)
RESET:
—
—
—
—
1
0
1. Bits 4 and 5 have test functions and should not be programmed.
2. Loaded from SHADOW byte.
Bits[7:4] are loaded at reset from the EEPROM SHADOW byte.
NOTE: Bits 5 and 4 are reserved for test purposes. These locations in the
SHADOW byte should not be programmed otherwise some locations in
the regular EEPROM array will no longer be visible.
NOBDML — Background Debug Mode Lockout Disable
0 = The BDM lockout is enabled.
1 = The BDM lockout is disabled.
Loaded from SHADOW byte at reset.
Read anytime. Write anytime in special modes (SMODN=0).
NOSHB — SHADOW Byte Disable
0 = SHADOW byte enabled and accessible at address $0FC0.
1 = Regular EEPROM array at address $0FC0.
Loaded from SHADOW byte at reset.
Read anytime. Write anytime in special modes (SMODN=0).
When NOSHB cleared, the regular EEPROM array byte at address
$0FC0 is no longer visible. The SHADOW byte is accessed instead
for both read and program/erase operations. BULK, ODD and EVEN
program/erase only apply if the SHADOW byte is enabled.
NOTE: Bit 6 of the SHADOW byte should not be cleared (set to ‘0’) in order to
have the full EEPROM array visible.
EESWAI — EEPROM Stops in Wait Mode
0 = The module is not affected during WAIT mode
1 = The module ceases to be clocked during WAIT mode
Read and write anytime.
NOTE: The EESWAI bit should be cleared if the WAIT mode vectors are
mapped in the EEPROM array.
Technical Data
MC68HC912DG128 — Rev 3.0
EEPROM Memory
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