Freescale Semiconductor, Inc.
Technical Data — MC68HC912DG128
Section 8. EEPROM Memory
8.1 Contents
8.2
8.3
8.4
8.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125
Future EEPROM Support . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .127
EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .128
8.2 Introduction
The MC68HC912DG128 EEPROM nonvolatile memory is arranged in a
16-bit configuration. The EEPROM array may be read as either bytes,
aligned words or misaligned words. Access times are one bus cycle for
byte and aligned word access and two bus cycles for misaligned word
operations.
Programming is by byte or aligned word. Attempts to program or erase
misaligned words will fail. Only the lower byte will be latched and
programmed or erased. Programming and erasing of the user EEPROM
can be done in all modes.
Each EEPROM byte or aligned word must be erased before
programming. The EEPROM module supports byte, aligned word, row
(32 bytes) or bulk erase, all using the internal charge pump. The
EEPROM module has hardware interlocks which protect stored data
from corruption by accidentally enabling the program/erase voltage.
Programming voltage is derived from the internal VDD supply with an
internal charge pump.
MC68HC912DG128 — Rev 3.0
Technical Data
EEPROM Memory
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