Freescale Semiconductor, Inc.
FLASH 2TS Memory
4.9 FLASH 2TS Block Protect Register
The block protect register (FLBPR) is implemented as a byte within the
FLASH 2TS memory. Each bit, when programmed, protects a range of
addresses in the FLASH 2TS.
Address: $FFF0
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
R
R
R
R
BPR3
BPR2
BPR1
BPR0
Unaffected by reset
R
= Reserved
Figure 4-3. FLASH 2TS Block Protect Register (FLBPR)
BPR3 — Block Protect Register Bit 3
This bit protects the memory contents in the address ranges
$7A00–$7FEF and $FFF0–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR2 — Block Protect Register Bit 2
This bit protects the memory contents in the address ranges
$7900–$7FEF and $FFF0–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR1 — Block Protect Register Bit 1
This bit protects the memory contents in the address ranges
$7880–$7FEF and $FFF0–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
BPR0 — Block Protect Register Bit 0
This bit protects the FLASH memory contents in the address ranges
$7800–$7FEF and $FFF0–$FFFF.
1 = Address range protected from erase or program
0 = Address range open to erase or program
Advance Information
52
MC68HC908RFRK2
FLASH 2TS Memory
MOTOROLA
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