Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
12.5 LVI Status Register
The LVI status register flags V voltages below theV
and V
LVS
DD
LVR
levels.
$FE0F
Address:
Bit 7
6
0
5
4
0
3
0
2
0
1
0
Bit 0
Read: LVIOUT
Write:
LOWV
0
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-2. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
The read-only flag becomes set when the V voltage falls below the
DD
V
voltage for 32 to 40 CGMXCLK cycles. Reset clears the LVIOUT
LVR
bit.
LOWV— LVI Low Indicator Bit
This read-only flag becomes set when the LVI is detecting V
DD
voltage below the V
threshold.
LVS
12.6 LVI Interrupts
The LVI module does not generate CPU interrupt requests.
12.7 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
Advance Information
172
MC68HC908RFRK2
MOTOROLA
Low-Voltage Inhibit (LVI)
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