Freescale Semiconductor, Inc.
Low-Voltage Inhibit (LVI)
Functional Description
12.4.1 False Trip Protection
The V pin level is digitally filtered to reduce false dead battery
DD
detection due to power supply noise. For the LVI module to reset due to
a low-power supply, V must remain at or below the V
level for a
LVR
DD
minimum 32–40 CGMXCLK cycles. See Table 12-1.
Table 12-1. LOWV Bit Indication
V
DD
Result
For Number of
At Level:
CGMXCLK Cycles:
Filter counter remains
clear
V
V
> V
ANY
DD
DD
LVR
LVR
No reset, continue
counting CGMXCLK
< V
< 32 CGMXCLK cycles
LVI may generate
a reset after
32 CGMXCLK cycles
Between 32 & 40 CGMXCLK
cycles
V
V
< V
< V
DD
DD
LVR
LVR
LVI is guaranteed to
generate a reset
> 40 CGMXCLK cycles
12.4.2 Short Stop Recovery Option
The LVI has an enable time of t . The system stabilization time for
EN
power-on reset and long stop recovery (both 4096 CGMXCLK cycles)
gives a delay longer than the LVI enable time for these startup
scenarios. There is no period where the MCU is not protected from a
low-power condition. However, when using the short stop recovery
configuration option, the 32 CGMXCLK delay must be greater than the
LVI turn on time to avoid a period in startup where the LVI is not
protecting the MCU.
NOTE: The LVI is enabled automatically after reset or stop recovery, if the
LVISTOP of the CONFIG register is set. (See Section 9. Configuration
Register (CONFIG).)
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
171
Low-Voltage Inhibit (LVI)
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
