Freescale Semiconductor, Inc.
Computer Operating Properly Module (COP)
COP Control Register
11.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
Low byte of reset vector
Clear COP counter
Unaffected by reset
Figure 11-2. COP Control Register (COPCTL)
11.6 Interrupts
The COP does not generate CPU interrupt requests.
11.7 Monitor Mode
The COP is disabled in monitor mode when V is present on the IRQ1
HI
pin or on the RST pin.
11.8 Low-Power Modes
The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.
11.8.1 Wait Mode
The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
Computer Operating Properly Module (COP)
167
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