Freescale Semiconductor, Inc.
Computer Operating Properly Module (COP)
I/O Signals
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler. If not cleared by software, the COP counter overflows and
13
4
18
4
generates an asynchronous reset after 2 – 2 or 2 – 2 CGMXCLK
cycles, depending on the state of the COP rate select bit, COPRS, in the
configuration register. When COPRS = 1, a 4.9152-MHz crystal gives a
COP timeout period of 53.3 ms. Writing any value to location $FFFF
before an overflow occurs prevents a COP reset by clearing the COP
counter and stages 5 through 12 of the prescaler.
NOTE: Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ1 pin is
held at V . During the break state, V on the RST pin disables the COP.
HI
HI
NOTE: Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
11.4 I/O Signals
The following paragraphs describe the signals shown in Figure 11-1.
11.4.1 CGMXCLK
CGMXCLK is the oscillator output signal. See 8.4.5 Clock Selection
Circuit for a description of CGMXCLK.
11.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
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Computer Operating Properly Module (COP)
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