Freescale Semiconductor, Inc.
Configuration Register (CONFIG)
Functional Description
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS. (See
Section 11. Computer Operating Properly Module (COP).)
13
4
1 = COP timeout period = 2 – 2 CGMXCLK cycles
18
4
0 = COP timeout period = 2 – 2 CGMXCLK cycles
SSREC — Short Stop Recovery Bit
SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
NOTE: Exiting stop mode by pulling reset will result in the long stop recovery.
If using the internal clock generator module or an external crystal
oscillator, do not set the SSREC bit.
The LVI has an enable time of t . The system stabilization time for
en
power-on reset and long stop recovery (both 4096 CGMXCLK cycles)
gives a delay longer than the LVI enable time for these startup
scenarios. There is no period where the MCU is not protected from a
low-power condition. However, when using the short stop recovery
configuration option, the 32 CGMXCLK delay must be greater than the
LVI’s turn on time to avoid a period in startup where the LVI is not
protecting the MCU.
STOP — STOP Instruction Enable Bit
STOP enables the STOP instruction.
1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode
COPD — COP Disable Bit
COPD disables the COP module. (See Section 11. Computer
Operating Properly Module (COP).)
1 = COP module disabled
0 = COP module enabled
MC68HC908RFRK2
MOTOROLA
AdvanceInformation
Configuration Register (CONFIG)
147
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