Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
13.9 SIOP Timing
(VDD = 4.5 Vdc ± 10%, VSS = 0 Vdc, TA = –40 °C to +125 °C, unless otherwise note)
8
2
Number
Characteristic
Operating Frequency
Symbol
Min
Max
Unit
Master
Slave
fSIOP(M)
fSIOP(S)
1
dc
1
1
fOP
3
Cycle Time
Master
1
tSCK(M)
tSCK(S)
1
—
1
1
tCYC
Slave
4
2
SCK Low Time
tCYC
tv
tHO
tS
238
—
—
200
—
ns
ns
ns
ns
ns
3
SDO Data Valid Time
SDO Hold Time
SDI Setup Time
SDI Hold Time
5
4
0
5
6
100
100
—
6
tH
—
NOTES:
7
1. fOP = fOSC ÷ 2 = 2.1 MHz max; tCYC = 1 ÷ fOP
2. In master mode, the SCK rate is determined by the programmable option in MOR1.
8
9
t2
t1
10
11
12
13
14
A
SCK
t5
t6
SDI
SDI
SDI
SDI
t3
t4
SDI
SDI
SDI
BIT 7
Figure 13-1. SIOP Timing Diagram
16
17
18
19
20
ELECTRICAL SPECIFICATIONS
Rev. 1.0
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