Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
TO VDD (OR STOP)
MCU
TO VDD (OR STOP)
MCU
8
2
OSC1
OSC2
OSC1
OSC2
3
4.7 MΩ
UNCONNECTED
4
EXTERNAL CLOCK
5
37 pF
37 pF
6
(b)
(a)
External Clock Source
Connections
Crystal or Ceramic
Resonator Connections
7
8
Figure 1-3. Oscillator Connections
9
1.4.4 Reset (RESET)
Driving this input low will reset the MCU to a known startup state. As an output,
the RESET pin indicates that an internal MCU reset has occurred. The RESET pin
contains an internal Schmitt trigger to improve its noise immunity. Refer to
SECTION 5 RESETS.
10
11
12
13
14
A
1.4.5 Port A (PA0 through PA7)
These eight I/O pins comprise port A. The state of any pin is software
programmable and all port A lines are configured as inputs during power-on or
reset. The pullups and interrupt options (active low) on the port A pins can be
individually programmed in the mask option register 2 (MOR2). For further
information, refer to SECTION 4 INTERRUPTS and SECTION 7 INPUT/OUTPUT
PORTS.
16
17
18
19
20
INTRODUCTION
MC68HC805P18
1-6
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