Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
8
2
COP
OSC 1
OSC 2
PH2
÷2
OSC
16-BIT TIMER
PD7/TCAP
TCMP
÷4
CPU CONTROL
68HC05 CPU
ALU
1 INPUT CAPTURE
1 OUTPUT COMPARE
PORT D LOGIC
RESET
IRQ
3
PD5/CKOUT
ACCUMULATOR
4
CPU REGISTERS
PC7/V
REFH
INDEX REGISTER
PC6/AD0
PC5/AD1
PC4/AD2
PC3/AD3
PC2
5
0 0 0 0 0 0 0 0 1 1 STK PNTR
M
C
PROGRAM COUNTER
6
COND CODE REG
1 1 1 H I N Z C
7
PC1
PC0
SRAM — 192 BYTES
8
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
9
USER EEPROM — 8064 BYTES
10
11
12
13
14
A
EEPROM — 128 BYTES
PORT B AND
SIOP
REGISTERS
AND LOGIC
PB5/SDO
PB6/SDI
PB7/SCK
V
DD
V
SS
Figure 1-1. Block Diagram
16
17
18
19
20
INTRODUCTION
MC68HC805P18
1-2
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