Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
1.3 Mask Options
8
2
EEPROM mask option register (MOR) selectable options include the following. For
additional information, refer to 8.4 Mask Option Registers (MOR).
• IRQ is edge- and level-sensitive or edge-sensitive only.
• SIOP most significant bit (MSB) first or least significant bit (LSB) first
• SIOP clock rate set to oscillator divided by 2, 4, 8, or 16
• COP watchdog timer enabled or disabled
3
4
• Stop instruction enabled or converted to halt mode
• Option to enable clock output pin to replace PD5
5
• Option to individually enable pullups/interrupts on each of the eight port A
pins
6
7
• LVR reset enabled or disabled
8
NOTE
9
A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low.
10
11
12
13
14
A
Any reference to voltage, current, or frequency specified in the
following sections will refer to the nominal values. The exact values
and their tolerance or limits are specified in SECTION 13
ELECTRICAL SPECIFICATIONS.
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17
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INTRODUCTION
Rev. 1.0
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