August 27, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
Page
6.3
6.4
DATA-RETENTION MODE.............................................................................. 6-4
SLOW MODE................................................................................................... 6-5
SECTION 7
INPUT/OUTPUT PORTS
7.1
PARALLEL PORTS.......................................................................................... 7-1
Port Data Registers ..................................................................................... 7-2
Port Data Direction Registers ...................................................................... 7-2
PORT A............................................................................................................ 7-2
PORT B............................................................................................................ 7-2
PORT C............................................................................................................ 7-2
7.1.1
7.1.2
7.2
7.3
7.4
SECTION 8
SYSTEM CLOCK
8.1
8.2
8.2.1
8.2.2
CLOCK SOURCES.......................................................................................... 8-1
VCO CLOCK SPEED....................................................................................... 8-2
VCO Slow Mode .......................................................................................... 8-2
Setting the VCO Speed ............................................................................... 8-3
SECTION 9
CORE TIMER
9.1
9.2
9.3
9.4
9.5
CORE TIMER STATUS AND CONTROL REGISTER..................................... 9-2
CORE TIMER COUNTER REGISTER (CTCR)............................................... 9-3
COP WATCHDOG........................................................................................... 9-4
CORE TIMER DURING WAIT MODE.............................................................. 9-5
CORE TIMER DURING STOP MODE............................................................. 9-5
SECTION 10
16-BIT TIMER
10.1 TIMER REGISTERS (TMRH, TMRL)............................................................. 10-2
10.2 ALTERNATE COUNTER REGISTERS (ACRH, ACRL) ................................ 10-4
10.3 INPUT CAPTURE REGISTERS .................................................................... 10-5
10.4 OUTPUT COMPARE REGISTERS ............................................................... 10-7
10.5 TIMER CONTROL REGISTER (TCR) ........................................................... 10-9
10.6 TIMER STATUS REGISTER (TSR)............................................................. 10-10
10.7 TIMER OPERATION DURING WAIT MODE............................................... 10-11
10.8 TIMER OPERATION DURING STOP MODE.............................................. 10-11
SECTION 11
PULSE WIDTH MODULATOR
11.1 D/A DATA REGISTERS (DAC0-DAC3)......................................................... 11-2
11.2 MUX CHANNEL ENABLE REGISTER (MCER) ............................................ 11-3
11.3 PWM DURING WAIT MODE ......................................................................... 11-4
11.4 PWM DURING STOP MODE......................................................................... 11-4
MC68HC05SB7
REV 2.1
MOTOROLA
iii
FREESCALE [ Freescale ]
