GENERAL RELEASE SPECIFICATION
August 27, 1998
TABLE OF CONTENTS
Section
Page
SECTION 4
INTERRUPTS
4.1
INTERRUPT VECTORS .................................................................................. 4-1
4.2
4.3
4.4
INTERRUPT PROCESSING............................................................................ 4-2
SOFTWARE INTERRUPT ............................................................................... 4-4
EXTERNAL INTERRUPT................................................................................. 4-4
IRQ/VPP Pin................................................................................................ 4-4
IRQ Status and Control Register (ISCR) ..................................................... 4-5
CORE TIMER INTERRUPTS........................................................................... 4-6
Core Timer Overflow Interrupt ..................................................................... 4-7
Real-Time Interrupt...................................................................................... 4-7
PROGRAMMABLE TIMER INTERRUPTS ...................................................... 4-7
Input Capture Interrupt................................................................................. 4-7
Output Compare Interrupt............................................................................ 4-7
Timer Overflow Interrupt.............................................................................. 4-7
SM-BUS INTERRUPT...................................................................................... 4-8
ANALOG INTERRUPTS .................................................................................. 4-8
Comparator Input Match Interrupt................................................................ 4-8
Input Capture Interrupt................................................................................. 4-8
CURRENT DETECT INTERRUPT................................................................... 4-8
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.6.3
4.7
4.8
4.8.1
4.8.2
4.9
SECTION 5
RESETS
5.1
5.2
5.3
POWER-ON RESET........................................................................................ 5-2
EXTERNAL RESET ......................................................................................... 5-2
INTERNAL RESETS........................................................................................ 5-2
Power-On Reset (POR)............................................................................... 5-2
Computer Operating Properly (COP) Reset ................................................ 5-3
Low Voltage Reset (LVR) ............................................................................ 5-4
Illegal Address Reset................................................................................... 5-4
RESET STATES .............................................................................................. 5-4
CPU ............................................................................................................. 5-4
I/O Registers................................................................................................ 5-4
Core Timer................................................................................................... 5-5
COP Watchdog............................................................................................ 5-5
16-Bit Programmable Timer......................................................................... 5-5
SM-Bus Serial Interface............................................................................... 5-5
Analog Subsystem....................................................................................... 5-6
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
SECTION 6
LOW POWER MODES
6.1
6.2
STOP MODE.................................................................................................... 6-3
WAIT MODE .................................................................................................... 6-4
MOTOROLA
ii
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
