GENERAL RELEASE SPECIFICATION
August 27, 1998
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4 channels 10-bit PWM running at a fixed clock rate
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2 ††
SM-Bus serial interface compatible with I C Bus
Slow ramp up power supply reset capability via LVR
Selectable sensitivity on IRQ interrupt (Edge- and Level-Sensitive or
Edge-Only)
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SM-Bus, current detect, 16-bit timer, analog subsystem and core timer
interrupts
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Internal 100kΩ pull-up resistor on RESET
Low Voltage Reset (LVR)
Illegal Address Reset
Computer Operating Properly (COP) Watchdog system
Available in 28-pin SSOP
NOTE
A bar over a signal name indicates an active low signal. For example, RESET is
active high and RESET is active low. Any reference to voltage, current, or
frequency specified in the following sections will refer to the nominal values. The
exact values and their tolerance or limits are specified in the Electrical
Specifications section.
1.2
1.3
MASK OPTION
A single mask option is available on the MC68HC05SB7.
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External oscillator on pins OSC1 and OSC2 (EPO):
[enabled or disabled]
PEPROM FACTORY PREPROGRAMMED OPTIONS
The MC68HC05SB7 is available with a factory preprogrammed PEPROM contain-
ing any of the following measured parameters:
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The internal VCO minimum frequency: programmed or left blank
The internal VCO maximum frequency: programmed or left blank
The internal bandgap reference voltage: programmed or left blank
The internal temperature sensor voltage at 80°C: programmed or left
blank
1.4
MCU STRUCTURE
The block diagram of the MC68HC05SB7 is shown in Figure 1-1.
SM-Bus is an Intel bus standard.
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†† 2
I C Bus is a Philips bus standard.
MOTOROLA
1-2
GENERAL DESCRIPTION
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
