August 27, 1998
GENERAL RELEASE SPECIFICATION
Internal
1
Reset
RESET
Pin
2
t
4096 t
CYC
RPD
Internal
3
Clock
Internal
Address
1FFF
NEW PCH NEW PCL
1FFE
3
Bus
Internal
Data
Bus
NEW
PCH
NEW
PCL
3
NOTES:
1. Represents the internal reset from low voltage reset, illegal opcode fetch or COP Watchdog timeout.
2. Normal delay of 4064 t
CYC.
3. Internal timing signal and data information not available externally.
Figure 18-2. Internal Reset Timing Diagram
V
V
DD
LVRH
V
LVRL
Low
Voltage
Reset
RESET
1
Pin
2
t
4096 t
CYC
RPD
Internal
3
Clock
Internal
Address
1FFF
NEW PCH NEW PCL
1FFE
3
Bus
Internal
Data
Bus
NEW
PCH
NEW
PCL
3
NOTES:
1. RESET pin pulled down be internal device.
2. Normal delay of 4064 t
CYC.
3. Internal timing signal and data information not available externally.
Figure 18-3. Low Voltage Reset Timing Diagram
MC68HC05SB7
REV 2.1
ELECTRICAL SPECIFICATIONS
MOTOROLA
18-7
FREESCALE [ Freescale ]
