GENERAL RELEASE SPECIFICATION
August 27, 1998
18.9 RESET CHARACTERISTICS
Characteristic
Symbol
Min
Typ
Max
Unit
Low Voltage Reset
Rising Recovery Voltage
Falling Reset Voltage
LVR Hysteresis
V
1.3
1.2
100
2.3
2.2
—
3.1
3.0
—
V
V
mV
LVRR
V
LVRF
LVRH
V
2
POR Recovery Voltage
V
0
—
100
mV
POR
2
POR V Slew Rate
DD
Rising
Falling
S
S
0.1
0.05
—
—
—
—
V/µs
V/µs
VDDR
VDDF
RESET Pulse Width (when bus clock active)
t
1.5
3
—
—
—
4
t
t
RL
CYC
CYC
RESET Pulldown Pulse Width (from internal reset)
t
RPD
NOTES:
1.
V
=5V ± 10%, V = 0 V, T ≤ T ≤ T , unless otherwise noted.
DD
SS
L
A
H
2. By design, not tested.
1
OSC1
t
RL
RESET
Internal
2
4096 t
CYC
3
Clock
Internal
Address
1FFE
1FFF
NEW PCH NEW PCL
3
Bus
Internal
Data
Bus
NEW
PCH
NEW
PCL
Op
code
3
NOTES:
1. Represents the internal gating of the OSC1 pin.
2. Normal delay of 4064 t
CYC.
3. Internal timing signal and data information not available externally.
Figure 18-1. Stop Recovery Timing Diagram
MOTOROLA
18-6
ELECTRICAL SPECIFICATIONS
MC68HC05SB7
REV 2.1
FREESCALE [ Freescale ]
