Freescale Semiconductor, Inc.
Ge ne ra l Re le a se Sp e c ific a tion — MC68HC705JJ7/ MC68HC705JP7
Se c tion 2. Me m ory
2.1 Conte nts
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Interrupt Vector Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
EPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
COP Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.2 Introd uc tion
2.3 Me m ory Ma p
This section describes the organization of the memory on the
MC68HC705JJ7/MC68HC705JP7.
The CPU can address 8 kilobytes of memory space as shown in
Figure 2-1. The EPROM portion of memory holds the program
instructions, fixed data, user defined vectors, and interrupt service
routines. The RAM portion of memory holds variable data. I/O registers
are memory mapped so that the CPU can access their locations in the
same way that it accesses all other memory locations.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Memory
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