Freescale Semiconductor, Inc.
Memory
Input/Output Registers
Addr.
Register
R/W Bit 7
6
5
4
3
2
1
Bit 0
Read:
* Port A & Port C Pulldown,
PDRA
$0010
Write: PDICH PDICL PDIA5
Read:
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
Port B Pulldown, PDRB
Timer Control, TCR
Write: PDIB7
PDIB6
PDIB5
PDIB4
0
PDIB3
0
PDIB2
0
PDIB1
IEDG
0
PDIB0
OLVL
0
Read:
ICIE
OCIE
TOIE
Write:
Read:
ICF
0
12
4
0
11
3
0
10
2
Timer Status, TSR
OCF
14
TOF
13
Write:
Read: BIT15
Write:
9
1
BIT8
BIT0
Input Capture MSB, ICRH
Input Capture LSB, ICRL
Output Compare MSB, OCRH
Output Compare LSB, OCRL
Timer Counter MSB, TMRH
Timer Counter LSB, TMRL
Read: BIT7
Write:
6
5
Read:
BIT15
Write:
14
13
12
11
10
9
BIT8
Read:
BIT7
6
5
4
3
2
1
9
BIT0
BIT8
Write:
Read: BIT15
Write:
14
13
12
11
10
Read: BIT7
Write:
6
14
6
5
13
5
4
12
4
3
11
3
2
10
2
1
9
1
BIT0
BIT8
BIT0
Read: BIT15
Write:
$001A Alternate. Counter MSB, ACRH
Read: BIT7
Write:
$001B
Alternate. Counter LSB, ACRL
Read:
Write:
Read:
Write:
0
0
0
0
0
$001C EPROM Programming, EPROG
ELAT
MPGM EPGM
R
R
R
R
$001D
$001E
$001F
Analog Control, ACR
Analog Status, ASR
Reserved
CHG
ATD2
CPF1
ATD1
ICEN
CPIE
CP2EN CP1EN
ISEN
Read: CPF2
Write:
0
0
CMP2
VOFF
CMP1
COE1
CPFR2 CPFR1
R
R
R
Read:
Write:
R
R
R
R
R
R
R
R
R
R
R
R
R
R
= Unimplemented
R
= Reserved
Figure 2-4. I/O Registers $0010–$001F
* Features related to port C are only available on the 28-pin MC68HC705JP7 devices.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Memory
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