Freescale Semiconductor, Inc.
Ge ne ra l De sc rip tion
1.8 RESET Pin
The RESET pin can be used as an input to reset the MCU to a known
startup state by pulling it to the low state. It also functions as an output
to indicate that an internal COP watchdog, illegal address, or low-voltage
reset has occurred. The RESET pin contains a pullup device to allow the
pin to be left disconnected without an external pullup resistor. The
RESET pin also contains a steering diode that, when the power is
removed, will discharge to V any charge left on an external capacitor
DD
connected between the RESET pin and V . The RESET pin also
SS
contains an internal Schmitt trigger to improve its noise immunity as an
input.
1.9 IRQ/ VPP Pin
The IRQ/V input pin drives the asynchronous IRQ interrupt function of
PP
the CPU. The IRQ interrupt function uses the LEVEL bit in the MOR to
provide either negative edge-sensitive triggering or both negative edge-
sensitive and low level-sensitive triggering. If the LEVEL bit is set to
enable level-sensitive triggering, the IRQ/V pin requires an external
PP
resistor to V for “wired-OR” operation. If the IRQ/V pin is not used,
DD
PP
it must be tied to the V supply. The IRQ/V pin contains an internal
DD
PP
Schmitt trigger as part of its input to improve noise immunity. The voltage
on this pin may affect the mode of operation if the voltage on the
IRQ/V pin is above V when the device is released from a reset
PP
DD
condition.
The IRQ/V pin may be taken above V in order to program an
PP
DD
EPROM memory location or personality EPROM bit. For more
information, refer to 15.14 PEPROM and EPROM Programming
Characteristics.
NOTE: Each of the PA0 through PA3 I/O pins may be connected as an OR
function with the IRQ interrupt function by the PIRQ bit in the MOR. This
capability allows keyboard scan applications where the transitions or
levels on the I/O pins will behave the same as the IRQ/V pin, except
PP
that active transitions and levels are inverted. The edge or level
sensitivity selected by the LEVEL bit in the MOR for the IRQ/V pin also
PP
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Description
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