Freescale Semiconductor, Inc.
Core Timer
COP Watchdog
COPC — COP Clear
This write-only bit resets the COP watchdog. The COP watchdog is
active in the run, wait, and halt modes of operation if the COP is
enabled by setting the COPEN bit in the MOR. The STOP instruction
disables the COP watchdog by clearing the counter and turning off its
clock source.
In applications that depend on the COP watchdog, the STOP
instruction can be disabled by setting the SWAIT bit in the MOR. In
applications that have wait cycles longer than the COP timeout
period, the COP watchdog can be disabled by clearing the COPEN
bit. Table 10-2 summarizes recommended conditions for enabling
and disabling the COP watchdog.
NOTE: If the voltage on the IRQ/V pin exceeds 1.5 × V , the COP watchdog
PP
DD
turns off and remains off until the IRQ/V pin voltage falls below
PP
1.5 × V
.
DD
Table 10-2. COP Watchdog Recommendations
SWAIT
Voltage on
Recommended COP
Watchdog Condition
Wait/Halt Time
1
IRQ/V Pin
(in MOR)
PP
2
Less than 1.5 × V
Less than 1.5 × V
Less than 1.5 × V
1
1
0
X
Less than COP Timeout Period
Greater than COP Timeout Period
Enabled
DD
DD
DD
Disabled
Disabled
Disabled
3
X
More than 1.5 × V
X
DD
NOTES:
1. The SWAIT bit in the MOR converts STOP instructions to HALT instructions.
2. Reset the COP watchdog immediately before executing the WAIT/HALT instruction.
3. X = don’t care.
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Core Timer
General Release Specification
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