Freescale Semiconductor, Inc.
Ana log Sub syste m
tDIS
tDIS
tDIS
tMAX
(MIN)
(MIN)
V
CAP
VMAX
tCHG
tCHG x ICHG
V
V =
X
X
CEXT
CHG
COMP2
TOF
OCF
ICF
0
2
3
4
5
1
Point
Action
Software/Hardware Action
Dependent Variable(s)
Begin initial discharge and select mode 0
by clearing the CHG, ATD2, and ATD1
control bits in the ACR.
0
Software write
Software
1
2
V
falls to V
.
Wait out minimum t
Software write
time
V
, I , C
MAX DIS EXT
CAP
SS
DIS
Stop discharge and begin charge by setting
CHG control bit in ACR.
Software
V
rises to V and comparator 2 output
X
trips, setting CPF2 and CMP2.
CAP
3
4
Wait out t
None
time
V , I
, C
CHG EXT
CHG
X
V
reaches V
.
V
, I
, C
CAP
MAX
MAX CHG EXT
Begin next discharge by clearing the CHG
control bit in the ACR. Reset CPF2 by
writing a “1” to CPFR2.
5
Software write
Software
Figure 8-8. A/D Conversion — Full Manual Control (Mode 0)
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Analog Subsystem
For More Information On This Product,
Go to: www.freescale.com
FREESCALE [ Freescale ]
