Freescale Semiconductor, Inc.
Analog Subsystem
A/D Conversion Methods
tDIS
tDIS
tDIS
(MIN)
(MIN)
V
CAP
VMAX
tCHG
tCHG x ICHG
V
V =
X
X
CEXT
CHG
COMP2
(TCAP)
TOF
OCF
ICF
0
1
2
3
1
2
Point
Action
Software/Hardware Action
Dependent Variable(s)
Begin initial discharge and select mode
3 by clearing CHG and setting ATD2
and ATD1 in the ACR. Also set ICEN
bit in ACR and IEDG bit in TCR.
0
Software write
Software
V
falls to V . Set timer output
SS
compare registers (OCRH and OCRL)
to desired charge start time.
CAP
Wait out minimum t
Software write to OCRH, OCRL.
time.
V
, I , C
software
,
DIS
MAX DIS
EXT
1
2
Stop discharge and begin charge when
the next OCF sets the CHG control bit
in ACR.
Timer OCF sets the CHG control Free-running timer
bit in the ACR. output compare, f
OSC
V
rises to V and comparator 2
X
CAP
output trips, setting CPF2 and CMP2,
which causes an ICF from the timer
and clears the CHG control bit in ACR.
Must clear CPF2 in order to trap next
CPF2 flag. Load next OCF.
Wait out t
Timer ICF clears the CHG
control bit in the ACR.
time.
CHG
3
V , I
, C
CHG EXT
X
Figure 8-11. A/D Conversion — OCF/ICF Control (Mode 3)
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
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