Freescale Semiconductor, Inc.
Ana log Sub syste m
tDIS
tDIS
tDIS
(MIN)
(MIN)
V
CAP
VMAX
tCHG
tCHG x ICHG
CEXT
V
V =
X
X
CHG
COMP2
(TCAP)
TOF
OCF
ICF
0
1
2
3
1
2
Point
Action
Software/Hardware Action
Dependent Variable(s)
Begin initial discharge and select mode
2 by clearing CHG and ATD1 and
setting ATD2 in the ACR. Also set
ICEN bit in ACR and IEDG bit in TCR.
0
Software write
Software
1
2
V
falls to V
.
Wait out minimum t
time
V
, I , C
MAX DIS EXT
CAP
SS
DIS
Stop discharge and begin charge when
the next TOF sets the CHG control bit
in ACR.
Timer TOF sets the CHG control Free-running timer
bit in the ACR. counter overflow, f
OSC
V
rises to V and comparator 2
X
CAP
output trips, setting CPF2 and CMP2,
which causes an ICF from the timer
and clears the CHG control bit in ACR.
Must clear CPF2 in order to trap next
CPF2 flag.
Wait out t
Timer ICF clears the CHG
control bit in the ACR.
time
CHG
3
V , I
, C
CHG EXT
X
Figure 8-10. A/D Conversion — TOF/ICF Control (Mode 2)
General Release Specification
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
Analog Subsystem
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