Freescale Semiconductor, Inc.
Analog Subsystem
Introduction
PB3/AN3/TCAP
2 TO 1
MUX
ITM RE
V
TCAP
DD
O
C
I
1
ICHG
PORTB
LOGIC
CHG
ATD1
ATD2
ISEN
CHARGE
CURRENT
CONTROL
LOGIC
PB0
AN0
IDISCHG
V
DD
CP2EN
ICEN
CP2EN
COMP2
(
A
+
-
INTERNAL
TEMPERATURE
DIODE
CP1EN
CPIE
INV
$001D
ANALOG
INTERRUPT
V
DD
CPF2
CPF1
CMP2
VREF
MUX1
SAMPLE
CAP
PORTB
LOGIC
CMP1
VOFF
PB1
AN1
100 MV
OFFSET
PORTB
LOGIC
$001E
PB2
AN2
CP1EN
OPT (MOR)
MUX2
MUX3
PORTB
LOGIC
+
-
HOLD
DHOLD
INV
COMP1
INV
PB3
AN3
TCAP
VREF
VREF
MUX4
MUX3
MUX2
MUX1
PORTB
LOGIC
PB4
AN4
TCMP
MUX4
PORT B
CONTROL
LOGIC
OLVL
V
COE1
OPT
AOFF
$0003
V
+
-
SS
MUX4
MUX3
MUX2
MUX1
DENOTES
INTERNAL
V
SS
ANALOG V
SS
Figure 8-1. Analog Subsystem Block Diagram
MC68HC705JJ7/MC68HC705JP7 — Rev. 3.0
General Release Specification
Analog Subsystem
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