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68HC705JJ7_1 参数 Datasheet PDF下载

68HC705JJ7_1图片预览
型号: 68HC705JJ7_1
PDF下载: 下载PDF文件 查看货源
内容描述: 常规版本规格 [General Release Specification]
分类和应用:
文件页数/大小: 230 页 / 5548 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
Ana log Sub syste m  
8.3 Ana log Multip le x Re g iste r  
The analog multiplex register (AMUX) controls the general  
interconnection and operation. The control bits in the AMUX are shown  
in Figure 8-2.  
$0003  
Read:  
Write:  
Reset:  
Bit 7  
HOLD  
1
6
DHOLD  
0
5
INV  
0
4
VREF  
0
3
MUX4  
0
2
MUX3  
0
1
MUX2  
0
Bit 0  
MUX1  
0
Figure 8-2. Analog Multiplex Register (AMUX)  
HOLD, DHOLD  
These read/write bits control the source connection to the negative  
input of voltage comparator 2 shown in Figure 8-3. This allows the  
voltage on the internal temperature sensing diode, the channel  
selection bus, or the divide-by-two channel selection bus to charge  
the internal sample capacitor and to also be presented to comparator  
2. The decoding of these sources is given in Table 8-1.  
During the hold case when both the HOLD and DHOLD bits are clear  
the VOFF bit in the Analog Status Register (ASR) can offset the V  
SS  
reference on the sample capacitor by approximately 100 mV. This  
offset source is bypassed whenever the sample capacitor is being  
charged with either the HOLD or DHOLD bit set. The VOFF bit must  
be enabled by the OPT bit in the COPR at location $1FF0.  
During a reset the HOLD bit is set and the DHOLD bit is cleared,  
which connects the internal sample capacitor to the channel selection  
bus. And since a reset also clears the MUX1:4 bits then the channel  
selection bus will be connected to V and the internal sample  
SS  
capacitor will be discharged to V following the reset.  
SS  
NOTE: When sampling a voltage for later conversion the HOLD and DHOLD bit  
should be cleared before making any changes in the MUX channel  
selection. If the MUX channel and the HOLD/DHOLD are changed on  
the same write cycle to the AMUX register, the sampled voltage may be  
altered during the channel switching.  
General Release Specification  
MC68HC705JJ7/MC68HC705JP7 Rev. 3.0  
Analog Subsystem  
For More Information On This Product,  
Go to: www.freescale.com  
 
 
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