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68HC05P4A_1 参数 Datasheet PDF下载

68HC05P4A_1图片预览
型号: 68HC05P4A_1
PDF下载: 下载PDF文件 查看货源
内容描述: 规格(通用版) [SPECIFICATION (General Release)]
分类和应用:
文件页数/大小: 83 页 / 2055 K
品牌: FREESCALE [ Freescale ]
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Freescale Semiconductor, Inc.  
GENERAL RELEASE SPECIFICATION  
11.1.2 Immediate  
Immediate instructions are those that contain a value to be used in an operation  
with the value in the accumulator or index register. Immediate instructions require  
no memory address and are two bytes long. The opcode is the first byte, and the  
immediate data value is the second byte.  
11.1.3 Direct  
Direct instructions can access any of the first 256 memory addresses with two  
bytes. The first byte is the opcode, and the second is the low byte of the operand  
address. In direct addressing, the CPU automatically uses $00 as the high byte of  
the operand address. BRSET and BRCLR are three-byte instructions that use  
direct addressing to access the operand and relative addressing to specify a  
branch destination.  
11.1.4 Extended  
Extended instructions use only three bytes to access any address in memory. The  
first byte is the opcode; the second and third bytes are the high and low bytes of  
the operand address.  
When using the Motorola assembler, the programmer does not need to specify  
whether an instruction is direct or extended. The assembler automatically selects  
the shortest form of the instruction.  
11.1.5 Indexed, No Offset  
Indexed instructions with no offset are one-byte instructions that can access data  
with variable addresses within the first 256 memory locations. The index register  
contains the low byte of the conditional address of the operand. The CPU  
automatically uses $00 as the high byte, so these instructions can address  
locations $0000–$00FF.  
Indexed, no offset instructions are often used to move a pointer through a table or  
to hold the address of a frequently used RAM or I/O location.  
11.1.6 Indexed, 8-Bit Offset  
Indexed, 8-bit offset instructions are two-byte instructions that can access data  
with variable addresses within the first 511 memory locations. The CPU adds the  
unsigned byte in the index register to the unsigned byte following the opcode. The  
sum is the conditional address of the operand. These instructions can access  
locations $0000–$01FE.  
INSTRUCTION SET  
MC68HC05P4A  
Rev. 2.0  
11-2  
For More Information On This Product,  
Go to: www.freescale.com  
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